Full example

Files corresponding to this example can be found into the examples/PLA directory of the PPart distribution. This file has been generated automatically by a high level tool []. It is a large circuit described in PLA format (82 Kb). The goal is to map it onto Xc4000 series. We want to simplify the circuit and minimize the size of the resulting layout. The circuit is a 6-bit adder with a special arithmetic. The circuit is available as a 12 inputs / 6-outputs PLA. We consider that 8 processors are available in the PVM machine.

The processing steps are the following :

• The PLA representation corresponds to a 6-nodes boolean network. Each node is associated to an output of the circuit. The corresponding boolean equations are very complex (fully specified). The first step consists in simplifying each equation, and splitting corresponding node into a set of smaller nodes. This is usefull for the subsequent steps of parallel synthesis since logic will be well distributed over the boolean network. To realize this first step, we split the network into 6 parts corresponding to the 6 nodes of the PLA representation, simplify each node in parallel and then collapse the resulting subnetworks.

  #########################
  # Pscript file PLA/pscript : 
  #########################
  
  pvm machine1 machine2 machine3 machine4 machine5 machine6 machine7 machine8
  verbose
  time 0
   
  # the circuit is a 6 outputs PLA --> 6 nodes
  # in the BLIF representation. Each node is first optimized
  # separatly using the SIS script described online.
  part 6 num6add.blif num6add
  6 source online
  simplify
  tech_decomp -a 4 -o 4
  end num6add num6add_d
  merge 6 num6add_2 num6add_d
   
  # standard synthesis (1P) is applied on 16 small partitions with
  # 8 processors, at a first optimization step.
  time 0
   
  part 16 num6add_d num6add_d
  16 source 1P num6add_d num6add_16
  merge 16 num6add_16 num6add_16
   
  # the circuit is re-synthesized with 8 partitions only, to
  # improve quality.
  time 0
  part 8 num6add_16 num6add_8
  8 source 1P num6add_8 num6add_opt
  merge 8 num6add_opt num6add_opt
  time 0

• The resulting network is very large. We are going to optimize it with an efficient but computation-intensive SIS script (1P). Thus we partition it into a lot of subnetworks (16) to reduce the runtime.
• The network is optimized, but lots of global optimizations have not been realized, since the number of partitions is large. Thus we re-apply the optimization and techonology mapping script with a smaller number of parts (8) to improve the final circuit quality.

These commands are stored in the pscript pscript. The synthesis could be started by the following command :

% ppart -f pscript

• Environment configuration
• Processing