Electronic circuit CAD tools are in charge of converting a description of a digital circuit into an interconnection of logic gates, namely a gate-level net-list (see fig 1).
Specifications can be seen as a hierarchy of behavioral,
register-transfer-level (RTL) and/or gate-level componants
descriptions. Compiling these descriptions for hardware involves several
stages as high level optimization, scheduling and sharing of resources. At
the RTL level, control and operators appear as an assembly of registers
and combinational circuits : memory elements are fixed, and logic is
represented as a set of boolean equations.
Logic synthesis is an optimization activity admitting RTL descriptions as an entry point. Its goal is to improve the circuit on criteria such as speed or area (logic optimization), and then to produce an equivalent specification suitable for a target technology such as ASIC or FPGA (technology mapping).
Generating a circuit involves others tasks depending on the technology. As an example, FPGAs need binding, placement, routing and configuration production (see fig 1).