As the FPGAs vendors are making much efforts to follow integration
technologies, the reconfigurable circuits become much larger, reaching the
100.000 gates, and much faster with system clock in excess of 100 MHz.
Reconfigurable computing will be an alternative for some computation
intensive applications. However, to be accepted, very important progresses
must be achieved in the programming methods : FPGA programming must be,
at least, comparable in speed to DSP assembly programming.
Figure: The CAD design process for FPGA target
Several bottlenecks limit the design process for FPGAs. To speed up the synthesis, attention must be paid to both the high level synthesis tools and the logic synthesis systems.
An Object-Oriented framework could provide a very interesting support on critical points such as CAD management and high level elementary circuits modeling. Our laboratory is developping an integrated environment for fast prototyping and co-design on FPGAs [10]. This environment is implemented using Smalltalk-80 on top of the Berkeley logic synthesis tools (SIS [6]). SIS is an open software for the synthesis of RTL circuits. It implements various algorithms, including logic minimization of boolean circuits (MisII), sequential circuits minimization, technology mapping for different targets such as FPGAs, testing, re-synthesis... SIS allows the use of different algorithms at each step of the synthesis according to the designer objectives. The synthesis process is described as a script corresponding to a sequence of synthesis tasks execution.