L. Lemarchand
Laboratoire d'Informatique de Brest,
Université de Bretagne Occidentale,
6 av. Le Gorgeu, Brest cedex 29287, France
e-mail: lemarch@univ-brest.fr
High level synthesis tools are the main stream today for the rapid design of electronic circuits. At a lower level, logic synthesis systems like SIS [6] are in charge of the optimization of the combinational part of the circuit. These tools also realize the mapping of the design on programmable devices such as FPGAs. The logic synthesis is a computation intensive task. We propose in this paper to partition the graph representing the circuit to reduce the synthesis problem size. Splitting decreases runtime and allows the use of more performant algorithms. However, it leads to a lost of quality for the final circuit. To perform an efficient partitioning, we have adapted an up-to-date algorithm, Metis [9], for the partitioning of circuit graphs.
Since subcircuits are processed separatly using SIS, a distributed implementation based on PVM [7] has also been realized. Results are very encouraging for both the runtime and the solution quality of the synthesis on a network of up to 8 workstations.