Logic synthesis of large circuits involves important runtime and huge memory
requirements, even if heuristics are used. The aim of the current work is to
improve execution time of the logic synthesis process. We focus on the
boolean part of RTL circuits. The set of equations describing the
circuit is represented by a boolean network. This network is a directed
acyclic graph (DAG). A node of this DAG is associated to each
boolean equation, and there is an arc between two nodes 
and 
if
the output of is an input to .
The proposed way to reduce the execution time of logic synthesis consists in partitioning the initial boolean network. After partitioning, each subnetwork is synthesized separatly. The problem size reduction is a very important point because common algorithms are often NP-Hard. Dividing the circuit also allows the use of more efficient algorithms. Furthermore, since subnetworks are considered as independant, synthesis can be parallelized easily.
However, the synthesis is no more global over the full network, whereas logic optimization and technology mapping are based on boolean properties and dependances between nodes. Since optimization relies partially on node relationships, partitioning leads to a lost of quality.